An inverter system that can realize a control with a high level by a microcontroller has widely been used for a control of a motor used in home electric appliances, such as an air-conditioner or a refrigerator, in order to enhance energy-saving performance, and an IPM (Intelligent Power Module) formed by packaging the switching element and its driver IC has widely been used for an inverter circuit that realizes the inverter system. As a wide bandgap semiconductor element such as SiCFET or GaNFET has been put into practical use, the incorporation of such wide bandgap semiconductor element into the IPM has been studied in order to enhance efficiency brought by low on-resistance and high-frequency characteristic of such wide bandgap semiconductor element.
FIG. 8 illustrates an example of a circuit structure of a conventional inverter circuit. FIG. 8 illustrates an example of a structure of an inverter circuit employing an IPM including a driver IC 30, n-type MOSFETs 7a and 7b, a diode 8, and a capacitor 9. The driver IC 30 has a function of a level shift circuit.
The driver IC 30 includes a power terminal Vcc and a ground terminal Vss which are externally supplied, a control input terminal Inh of a high-side circuit 36, a control input terminal Inl on a low-side, a positive voltage power terminal Vb, a reference power terminal Vs, and an output terminal Vh of the high-side circuit 36, and an output terminal Vl on the low-side. The power terminal Vcc and the ground terminal Vss of the driver IC 30 are connected respectively to a power terminal VCC and a ground terminal VSS of the IPM.
A control input signal of the high-side circuit 36 inputted from the control input terminal Inh is connected to an input terminal IN of a pulse generating circuit 31. A first control pulse with a pulse width of about 100 ns is generated from a first output terminal OUT1 after a rising of the control input signal, while a second control pulse with a pulse width of about 100 ns is generated from a second output terminal OUT2 after a falling of the control input signal.
FIG. 9 illustrates an example of a circuit structure of the pulse generating circuit 31. The pulse generating circuit 31 includes six cascade-connected inverters 41a, 41b, 41c, 41d, 41e, and 41f, two NAND circuits 42a and 42b, two inverters 43a and 43b, and two capacitors 44a and 44b for setting a pulse width. An input of the head inverter 41a is connected to the input terminal IN. When an output node of each of the inverters 41a, 41b, 41c, 41d, 41e, and 41f is defined as N1, N2, N3, N4, N5, and N6 in order from head to tail, one end of each of the capacitors 44a and 44b is grounded, the other ends of the capacitors 44a and 44b are connected to the nodes N3 and N4 respectively, the nodes N2 and N5 are connected to two inputs of the NAND circuit 42a respectively, the nodes N1 and N6 are connected to two inputs of the NAND circuit 42b respectively, outputs of the NAND circuits 42a and 42b are connected to inputs of the inverters 43a and 43b respectively, and outputs of the inverters 43a and 43b are connected to output terminals OUT1 and OUT2 respectively.
FIG. 10 illustrates an operation waveform of the pulse generating circuit 31. The first pulse in synchronization with the rising of the control input signal inputted to the input terminal IN is outputted from the first output terminal OUT1, while the second pulse in synchronization with the falling of the control input signal is outputted from the second output terminal OUT2.
The first pulse is inputted to a gate of the n-type MOSFET 32a, is converted into a signal whose level is shifted by a resistance 33a, and is inputted to a reset input R of an RS flip-flop 34. The second pulse is inputted to a gate of the n-type MOSFET 32b, is converted into a signal whose level is shifted by a resistance 33b, and is inputted to a set input S of the RS flip-flop 34. An output Q of the RS flip-flop 34 is connected to an input of an inverter 35, and an output of the inverter 35 is connected to a gate of a MOSFET 7a via an output terminal Vh.
As a result, the control input signal inputted to the control input terminal Inh is transmitted to the high-side circuit 36, which is floating, with its level being shifted, and is outputted to the gate of the MOSFET 7a as a high-side output signal. On the other hand, the control input signal on the low-side inputted to the control input terminal Inl on the low-side is outputted to the gate terminal of the MOSFET 7b via the output terminal Vl on the low-side.
A high-voltage power supply of about 600 V is connected to a drain of the MOSFET 7a via a high-voltage power terminal HV in the IPM, for example. The source of the MOSFET 7a and the drain of the MOSFET 7b are connected to the reference power terminal Vs of the driver IC 30 and an output terminal OUT of the IPM. The source of the MOSFET 7b is connected to an output ground terminal GND of the IPM to be grounded.
One end of the capacitor 9 is connected to a cathode terminal of the diode 8 and the positive-voltage power terminal Vb, the other end of the capacitor 9 is connected to the reference power terminal Vs, and an anode terminal of the diode 8 is connected to the power terminal Vcc. The diode 8 and the capacitor 9 constitute a bootstrap circuit. When the power-supply voltage supplied via the power terminal VCC of the IPM connected to the power terminal Vcc is charged to the floating capacitor 9, and the potential of the reference power terminal Vs rises via the MOSFET 7a, a high voltage is generated on the positive voltage power terminal Vb by capacitive coupling via the capacitor 9, whereby floating electric supply to the high-side circuit 36 is realized.
When two control input signals having opposite phases, are inputted to the control input terminals Inh and Inl respectively, an output signal having the high voltage applied between the power terminal HV of the IPM and the ground terminal GND as an amplitude is generated on the output terminal OUT of the IPM connected to the reference power terminal Vs.
The reason why the pulse generating circuit 31 and the RS flip-flop 34 are used in the conventional circuit structure illustrated in FIG. 8 is to suppress the power consumption on the high-side circuit 36 as much as possible and to keep the output capability of the inverter 35, since the bootstrap circuit has a limitation on power to be supplied to the capacitor 9.
However, the conventional circuit structure has a problem that the input of the RS flip-flop 34 is liable to malfunction to noise. Under the condition with a lot of noise such as the high-side circuit 36, a measure against noise is required. In view of this problem, Patent Document 1 proposes a circuit structure in which a filter configured with a logical circuit is provided in front of the RS flip-flop to prevent the malfunction caused by noise.